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Update vendor folder (Delve support)
This commit is contained in:
Faissal Elamraoui
643
vendor/rsc.io/x86/x86asm/inst.go
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vendored
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643
vendor/rsc.io/x86/x86asm/inst.go
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vendored
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@ -0,0 +1,643 @@
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// Copyright 2014 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Package x86asm implements decoding of x86 machine code.
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package x86asm
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import (
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"bytes"
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"fmt"
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)
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// An Inst is a single instruction.
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type Inst struct {
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Prefix Prefixes // Prefixes applied to the instruction.
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Op Op // Opcode mnemonic
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Opcode uint32 // Encoded opcode bits, left aligned (first byte is Opcode>>24, etc)
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Args Args // Instruction arguments, in Intel order
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Mode int // processor mode in bits: 16, 32, or 64
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AddrSize int // address size in bits: 16, 32, or 64
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DataSize int // operand size in bits: 16, 32, or 64
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MemBytes int // size of memory argument in bytes: 1, 2, 4, 8, 16, and so on.
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Len int // length of encoded instruction in bytes
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PCRel int // length of PC-relative address in instruction encoding
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PCRelOff int // index of start of PC-relative address in instruction encoding
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}
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// Prefixes is an array of prefixes associated with a single instruction.
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// The prefixes are listed in the same order as found in the instruction:
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// each prefix byte corresponds to one slot in the array. The first zero
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// in the array marks the end of the prefixes.
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type Prefixes [14]Prefix
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// A Prefix represents an Intel instruction prefix.
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// The low 8 bits are the actual prefix byte encoding,
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// and the top 8 bits contain distinguishing bits and metadata.
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type Prefix uint16
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const (
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// Metadata about the role of a prefix in an instruction.
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PrefixImplicit Prefix = 0x8000 // prefix is implied by instruction text
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PrefixIgnored Prefix = 0x4000 // prefix is ignored: either irrelevant or overridden by a later prefix
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PrefixInvalid Prefix = 0x2000 // prefix makes entire instruction invalid (bad LOCK)
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// Memory segment overrides.
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PrefixES Prefix = 0x26 // ES segment override
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PrefixCS Prefix = 0x2E // CS segment override
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PrefixSS Prefix = 0x36 // SS segment override
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PrefixDS Prefix = 0x3E // DS segment override
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PrefixFS Prefix = 0x64 // FS segment override
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PrefixGS Prefix = 0x65 // GS segment override
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// Branch prediction.
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PrefixPN Prefix = 0x12E // predict not taken (conditional branch only)
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PrefixPT Prefix = 0x13E // predict taken (conditional branch only)
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// Size attributes.
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PrefixDataSize Prefix = 0x66 // operand size override
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PrefixData16 Prefix = 0x166
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PrefixData32 Prefix = 0x266
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PrefixAddrSize Prefix = 0x67 // address size override
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PrefixAddr16 Prefix = 0x167
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PrefixAddr32 Prefix = 0x267
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// One of a kind.
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PrefixLOCK Prefix = 0xF0 // lock
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PrefixREPN Prefix = 0xF2 // repeat not zero
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PrefixXACQUIRE Prefix = 0x1F2
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PrefixBND Prefix = 0x2F2
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PrefixREP Prefix = 0xF3 // repeat
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PrefixXRELEASE Prefix = 0x1F3
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// The REX prefixes must be in the range [PrefixREX, PrefixREX+0x10).
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// the other bits are set or not according to the intended use.
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PrefixREX Prefix = 0x40 // REX 64-bit extension prefix
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PrefixREXW Prefix = 0x08 // extension bit W (64-bit instruction width)
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PrefixREXR Prefix = 0x04 // extension bit R (r field in modrm)
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PrefixREXX Prefix = 0x02 // extension bit X (index field in sib)
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PrefixREXB Prefix = 0x01 // extension bit B (r/m field in modrm or base field in sib)
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)
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// IsREX reports whether p is a REX prefix byte.
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func (p Prefix) IsREX() bool {
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return p&0xF0 == PrefixREX
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}
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func (p Prefix) String() string {
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p &^= PrefixImplicit | PrefixIgnored | PrefixInvalid
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if s := prefixNames[p]; s != "" {
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return s
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}
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if p.IsREX() {
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s := "REX."
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if p&PrefixREXW != 0 {
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s += "W"
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}
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if p&PrefixREXR != 0 {
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s += "R"
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}
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if p&PrefixREXX != 0 {
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s += "X"
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}
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if p&PrefixREXB != 0 {
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s += "B"
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}
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return s
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}
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return fmt.Sprintf("Prefix(%#x)", int(p))
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}
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// An Op is an x86 opcode.
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type Op uint32
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func (op Op) String() string {
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i := int(op)
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if i < 0 || i >= len(opNames) || opNames[i] == "" {
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return fmt.Sprintf("Op(%d)", i)
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}
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return opNames[i]
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}
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// An Args holds the instruction arguments.
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// If an instruction has fewer than 4 arguments,
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// the final elements in the array are nil.
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type Args [4]Arg
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// An Arg is a single instruction argument,
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// one of these types: Reg, Mem, Imm, Rel.
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type Arg interface {
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String() string
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isArg()
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}
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// Note that the implements of Arg that follow are all sized
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// so that on a 64-bit machine the data can be inlined in
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// the interface value instead of requiring an allocation.
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// A Reg is a single register.
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// The zero Reg value has no name but indicates ``no register.''
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type Reg uint8
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const (
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_ Reg = iota
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// 8-bit
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AL
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CL
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DL
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BL
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AH
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CH
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DH
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BH
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SPB
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BPB
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SIB
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DIB
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R8B
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R9B
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R10B
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R11B
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R12B
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R13B
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R14B
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R15B
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// 16-bit
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AX
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CX
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DX
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BX
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SP
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BP
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SI
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DI
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R8W
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R9W
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R10W
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R11W
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R12W
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R13W
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R14W
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R15W
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// 32-bit
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EAX
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ECX
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EDX
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EBX
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ESP
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EBP
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ESI
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EDI
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R8L
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R9L
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R10L
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R11L
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R12L
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R13L
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R14L
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R15L
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// 64-bit
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RAX
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RCX
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RDX
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RBX
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RSP
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RBP
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RSI
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RDI
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R8
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R9
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R10
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R11
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R12
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R13
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R14
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R15
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// Instruction pointer.
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IP // 16-bit
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EIP // 32-bit
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RIP // 64-bit
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// 387 floating point registers.
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F0
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F1
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F2
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F3
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F4
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F5
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F6
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F7
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// MMX registers.
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M0
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M1
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M2
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M3
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M4
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M5
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||||
M6
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M7
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||||
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// XMM registers.
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X0
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X1
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X2
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X3
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X4
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X5
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X6
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X7
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X8
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X9
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X10
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X11
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X12
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X13
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||||
X14
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X15
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// Segment registers.
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ES
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CS
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SS
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DS
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FS
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GS
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// System registers.
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GDTR
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IDTR
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LDTR
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MSW
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TASK
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// Control registers.
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CR0
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CR1
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CR2
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CR3
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CR4
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CR5
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CR6
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CR7
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CR8
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CR9
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||||
CR10
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||||
CR11
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||||
CR12
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||||
CR13
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||||
CR14
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||||
CR15
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||||
|
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// Debug registers.
|
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DR0
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DR1
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DR2
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DR3
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DR4
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DR5
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DR6
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DR7
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||||
DR8
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DR9
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||||
DR10
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||||
DR11
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||||
DR12
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||||
DR13
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||||
DR14
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||||
DR15
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||||
|
||||
// Task registers.
|
||||
TR0
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TR1
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||||
TR2
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TR3
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TR4
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TR5
|
||||
TR6
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TR7
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)
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|
||||
const regMax = TR7
|
||||
|
||||
func (Reg) isArg() {}
|
||||
|
||||
func (r Reg) String() string {
|
||||
i := int(r)
|
||||
if i < 0 || i >= len(regNames) || regNames[i] == "" {
|
||||
return fmt.Sprintf("Reg(%d)", i)
|
||||
}
|
||||
return regNames[i]
|
||||
}
|
||||
|
||||
// A Mem is a memory reference.
|
||||
// The general form is Segment:[Base+Scale*Index+Disp].
|
||||
type Mem struct {
|
||||
Segment Reg
|
||||
Base Reg
|
||||
Scale uint8
|
||||
Index Reg
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||||
Disp int64
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||||
}
|
||||
|
||||
func (Mem) isArg() {}
|
||||
|
||||
func (m Mem) String() string {
|
||||
var base, plus, scale, index, disp string
|
||||
|
||||
if m.Base != 0 {
|
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base = m.Base.String()
|
||||
}
|
||||
if m.Scale != 0 {
|
||||
if m.Base != 0 {
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plus = "+"
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}
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if m.Scale > 1 {
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scale = fmt.Sprintf("%d*", m.Scale)
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}
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index = m.Index.String()
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||||
}
|
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if m.Disp != 0 || m.Base == 0 && m.Scale == 0 {
|
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disp = fmt.Sprintf("%+#x", m.Disp)
|
||||
}
|
||||
return "[" + base + plus + scale + index + disp + "]"
|
||||
}
|
||||
|
||||
// A Rel is an offset relative to the current instruction pointer.
|
||||
type Rel int32
|
||||
|
||||
func (Rel) isArg() {}
|
||||
|
||||
func (r Rel) String() string {
|
||||
return fmt.Sprintf(".%+d", r)
|
||||
}
|
||||
|
||||
// An Imm is an integer constant.
|
||||
type Imm int64
|
||||
|
||||
func (Imm) isArg() {}
|
||||
|
||||
func (i Imm) String() string {
|
||||
return fmt.Sprintf("%#x", int64(i))
|
||||
}
|
||||
|
||||
func (i Inst) String() string {
|
||||
var buf bytes.Buffer
|
||||
for _, p := range i.Prefix {
|
||||
if p == 0 {
|
||||
break
|
||||
}
|
||||
if p&PrefixImplicit != 0 {
|
||||
continue
|
||||
}
|
||||
fmt.Fprintf(&buf, "%v ", p)
|
||||
}
|
||||
fmt.Fprintf(&buf, "%v", i.Op)
|
||||
sep := " "
|
||||
for _, v := range i.Args {
|
||||
if v == nil {
|
||||
break
|
||||
}
|
||||
fmt.Fprintf(&buf, "%s%v", sep, v)
|
||||
sep = ", "
|
||||
}
|
||||
return buf.String()
|
||||
}
|
||||
|
||||
func isReg(a Arg) bool {
|
||||
_, ok := a.(Reg)
|
||||
return ok
|
||||
}
|
||||
|
||||
func isSegReg(a Arg) bool {
|
||||
r, ok := a.(Reg)
|
||||
return ok && ES <= r && r <= GS
|
||||
}
|
||||
|
||||
func isMem(a Arg) bool {
|
||||
_, ok := a.(Mem)
|
||||
return ok
|
||||
}
|
||||
|
||||
func isImm(a Arg) bool {
|
||||
_, ok := a.(Imm)
|
||||
return ok
|
||||
}
|
||||
|
||||
func regBytes(a Arg) int {
|
||||
r, ok := a.(Reg)
|
||||
if !ok {
|
||||
return 0
|
||||
}
|
||||
if AL <= r && r <= R15B {
|
||||
return 1
|
||||
}
|
||||
if AX <= r && r <= R15W {
|
||||
return 2
|
||||
}
|
||||
if EAX <= r && r <= R15L {
|
||||
return 4
|
||||
}
|
||||
if RAX <= r && r <= R15 {
|
||||
return 8
|
||||
}
|
||||
return 0
|
||||
}
|
||||
|
||||
func isSegment(p Prefix) bool {
|
||||
switch p {
|
||||
case PrefixCS, PrefixDS, PrefixES, PrefixFS, PrefixGS, PrefixSS:
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
|
||||
// The Op definitions and string list are in tables.go.
|
||||
|
||||
var prefixNames = map[Prefix]string{
|
||||
PrefixCS: "CS",
|
||||
PrefixDS: "DS",
|
||||
PrefixES: "ES",
|
||||
PrefixFS: "FS",
|
||||
PrefixGS: "GS",
|
||||
PrefixSS: "SS",
|
||||
PrefixLOCK: "LOCK",
|
||||
PrefixREP: "REP",
|
||||
PrefixREPN: "REPN",
|
||||
PrefixAddrSize: "ADDRSIZE",
|
||||
PrefixDataSize: "DATASIZE",
|
||||
PrefixAddr16: "ADDR16",
|
||||
PrefixData16: "DATA16",
|
||||
PrefixAddr32: "ADDR32",
|
||||
PrefixData32: "DATA32",
|
||||
PrefixBND: "BND",
|
||||
PrefixXACQUIRE: "XACQUIRE",
|
||||
PrefixXRELEASE: "XRELEASE",
|
||||
PrefixREX: "REX",
|
||||
PrefixPT: "PT",
|
||||
PrefixPN: "PN",
|
||||
}
|
||||
|
||||
var regNames = [...]string{
|
||||
AL: "AL",
|
||||
CL: "CL",
|
||||
BL: "BL",
|
||||
DL: "DL",
|
||||
AH: "AH",
|
||||
CH: "CH",
|
||||
BH: "BH",
|
||||
DH: "DH",
|
||||
SPB: "SPB",
|
||||
BPB: "BPB",
|
||||
SIB: "SIB",
|
||||
DIB: "DIB",
|
||||
R8B: "R8B",
|
||||
R9B: "R9B",
|
||||
R10B: "R10B",
|
||||
R11B: "R11B",
|
||||
R12B: "R12B",
|
||||
R13B: "R13B",
|
||||
R14B: "R14B",
|
||||
R15B: "R15B",
|
||||
AX: "AX",
|
||||
CX: "CX",
|
||||
BX: "BX",
|
||||
DX: "DX",
|
||||
SP: "SP",
|
||||
BP: "BP",
|
||||
SI: "SI",
|
||||
DI: "DI",
|
||||
R8W: "R8W",
|
||||
R9W: "R9W",
|
||||
R10W: "R10W",
|
||||
R11W: "R11W",
|
||||
R12W: "R12W",
|
||||
R13W: "R13W",
|
||||
R14W: "R14W",
|
||||
R15W: "R15W",
|
||||
EAX: "EAX",
|
||||
ECX: "ECX",
|
||||
EDX: "EDX",
|
||||
EBX: "EBX",
|
||||
ESP: "ESP",
|
||||
EBP: "EBP",
|
||||
ESI: "ESI",
|
||||
EDI: "EDI",
|
||||
R8L: "R8L",
|
||||
R9L: "R9L",
|
||||
R10L: "R10L",
|
||||
R11L: "R11L",
|
||||
R12L: "R12L",
|
||||
R13L: "R13L",
|
||||
R14L: "R14L",
|
||||
R15L: "R15L",
|
||||
RAX: "RAX",
|
||||
RCX: "RCX",
|
||||
RDX: "RDX",
|
||||
RBX: "RBX",
|
||||
RSP: "RSP",
|
||||
RBP: "RBP",
|
||||
RSI: "RSI",
|
||||
RDI: "RDI",
|
||||
R8: "R8",
|
||||
R9: "R9",
|
||||
R10: "R10",
|
||||
R11: "R11",
|
||||
R12: "R12",
|
||||
R13: "R13",
|
||||
R14: "R14",
|
||||
R15: "R15",
|
||||
IP: "IP",
|
||||
EIP: "EIP",
|
||||
RIP: "RIP",
|
||||
F0: "F0",
|
||||
F1: "F1",
|
||||
F2: "F2",
|
||||
F3: "F3",
|
||||
F4: "F4",
|
||||
F5: "F5",
|
||||
F6: "F6",
|
||||
F7: "F7",
|
||||
M0: "M0",
|
||||
M1: "M1",
|
||||
M2: "M2",
|
||||
M3: "M3",
|
||||
M4: "M4",
|
||||
M5: "M5",
|
||||
M6: "M6",
|
||||
M7: "M7",
|
||||
X0: "X0",
|
||||
X1: "X1",
|
||||
X2: "X2",
|
||||
X3: "X3",
|
||||
X4: "X4",
|
||||
X5: "X5",
|
||||
X6: "X6",
|
||||
X7: "X7",
|
||||
X8: "X8",
|
||||
X9: "X9",
|
||||
X10: "X10",
|
||||
X11: "X11",
|
||||
X12: "X12",
|
||||
X13: "X13",
|
||||
X14: "X14",
|
||||
X15: "X15",
|
||||
CS: "CS",
|
||||
SS: "SS",
|
||||
DS: "DS",
|
||||
ES: "ES",
|
||||
FS: "FS",
|
||||
GS: "GS",
|
||||
GDTR: "GDTR",
|
||||
IDTR: "IDTR",
|
||||
LDTR: "LDTR",
|
||||
MSW: "MSW",
|
||||
TASK: "TASK",
|
||||
CR0: "CR0",
|
||||
CR1: "CR1",
|
||||
CR2: "CR2",
|
||||
CR3: "CR3",
|
||||
CR4: "CR4",
|
||||
CR5: "CR5",
|
||||
CR6: "CR6",
|
||||
CR7: "CR7",
|
||||
CR8: "CR8",
|
||||
CR9: "CR9",
|
||||
CR10: "CR10",
|
||||
CR11: "CR11",
|
||||
CR12: "CR12",
|
||||
CR13: "CR13",
|
||||
CR14: "CR14",
|
||||
CR15: "CR15",
|
||||
DR0: "DR0",
|
||||
DR1: "DR1",
|
||||
DR2: "DR2",
|
||||
DR3: "DR3",
|
||||
DR4: "DR4",
|
||||
DR5: "DR5",
|
||||
DR6: "DR6",
|
||||
DR7: "DR7",
|
||||
DR8: "DR8",
|
||||
DR9: "DR9",
|
||||
DR10: "DR10",
|
||||
DR11: "DR11",
|
||||
DR12: "DR12",
|
||||
DR13: "DR13",
|
||||
DR14: "DR14",
|
||||
DR15: "DR15",
|
||||
TR0: "TR0",
|
||||
TR1: "TR1",
|
||||
TR2: "TR2",
|
||||
TR3: "TR3",
|
||||
TR4: "TR4",
|
||||
TR5: "TR5",
|
||||
TR6: "TR6",
|
||||
TR7: "TR7",
|
||||
}
|
||||
Reference in New Issue
Block a user