mirror of
https://github.com/beego/bee.git
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519 lines
10 KiB
Go
519 lines
10 KiB
Go
// Copyright 2014 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package x86asm
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import (
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"fmt"
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"strings"
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)
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// IntelSyntax returns the Intel assembler syntax for the instruction, as defined by Intel's XED tool.
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func IntelSyntax(inst Inst) string {
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var iargs []Arg
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for _, a := range inst.Args {
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if a == nil {
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break
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}
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iargs = append(iargs, a)
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}
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switch inst.Op {
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case INSB, INSD, INSW, OUTSB, OUTSD, OUTSW, LOOPNE, JCXZ, JECXZ, JRCXZ, LOOP, LOOPE, MOV, XLATB:
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if inst.Op == MOV && (inst.Opcode>>16)&0xFFFC != 0x0F20 {
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break
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}
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for i, p := range inst.Prefix {
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if p&0xFF == PrefixAddrSize {
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inst.Prefix[i] &^= PrefixImplicit
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}
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}
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}
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switch inst.Op {
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case MOV:
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dst, _ := inst.Args[0].(Reg)
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src, _ := inst.Args[1].(Reg)
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if ES <= dst && dst <= GS && EAX <= src && src <= R15L {
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src -= EAX - AX
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iargs[1] = src
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}
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if ES <= dst && dst <= GS && RAX <= src && src <= R15 {
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src -= RAX - AX
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iargs[1] = src
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}
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if inst.Opcode>>24&^3 == 0xA0 {
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for i, p := range inst.Prefix {
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if p&0xFF == PrefixAddrSize {
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inst.Prefix[i] |= PrefixImplicit
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}
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}
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}
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}
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switch inst.Op {
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case AAM, AAD:
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if imm, ok := iargs[0].(Imm); ok {
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if inst.DataSize == 32 {
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iargs[0] = Imm(uint32(int8(imm)))
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} else if inst.DataSize == 16 {
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iargs[0] = Imm(uint16(int8(imm)))
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}
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}
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case PUSH:
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if imm, ok := iargs[0].(Imm); ok {
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iargs[0] = Imm(uint32(imm))
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}
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}
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for _, p := range inst.Prefix {
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if p&PrefixImplicit != 0 {
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for j, pj := range inst.Prefix {
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if pj&0xFF == p&0xFF {
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inst.Prefix[j] |= PrefixImplicit
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}
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}
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}
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}
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if inst.Op != 0 {
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for i, p := range inst.Prefix {
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switch p &^ PrefixIgnored {
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case PrefixData16, PrefixData32, PrefixCS, PrefixDS, PrefixES, PrefixSS:
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inst.Prefix[i] |= PrefixImplicit
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}
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if p.IsREX() {
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inst.Prefix[i] |= PrefixImplicit
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}
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}
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}
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if isLoop[inst.Op] || inst.Op == JCXZ || inst.Op == JECXZ || inst.Op == JRCXZ {
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for i, p := range inst.Prefix {
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if p == PrefixPT || p == PrefixPN {
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inst.Prefix[i] |= PrefixImplicit
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}
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}
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}
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switch inst.Op {
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case AAA, AAS, CBW, CDQE, CLC, CLD, CLI, CLTS, CMC, CPUID, CQO, CWD, DAA, DAS,
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FDECSTP, FINCSTP, FNCLEX, FNINIT, FNOP, FWAIT, HLT,
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ICEBP, INSB, INSD, INSW, INT, INTO, INVD, IRET, IRETQ,
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LAHF, LEAVE, LRET, MONITOR, MWAIT, NOP, OUTSB, OUTSD, OUTSW,
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PAUSE, POPA, POPF, POPFQ, PUSHA, PUSHF, PUSHFQ,
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RDMSR, RDPMC, RDTSC, RDTSCP, RET, RSM,
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SAHF, STC, STD, STI, SYSENTER, SYSEXIT, SYSRET,
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UD2, WBINVD, WRMSR, XEND, XLATB, XTEST:
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if inst.Op == NOP && inst.Opcode>>24 != 0x90 {
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break
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}
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if inst.Op == RET && inst.Opcode>>24 != 0xC3 {
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break
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}
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if inst.Op == INT && inst.Opcode>>24 != 0xCC {
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break
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}
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if inst.Op == LRET && inst.Opcode>>24 != 0xcb {
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break
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}
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for i, p := range inst.Prefix {
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if p&0xFF == PrefixDataSize {
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inst.Prefix[i] &^= PrefixImplicit | PrefixIgnored
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}
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}
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case 0:
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// ok
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}
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switch inst.Op {
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case INSB, INSD, INSW, OUTSB, OUTSD, OUTSW, MONITOR, MWAIT, XLATB:
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iargs = nil
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case STOSB, STOSW, STOSD, STOSQ:
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iargs = iargs[:1]
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case LODSB, LODSW, LODSD, LODSQ, SCASB, SCASW, SCASD, SCASQ:
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iargs = iargs[1:]
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}
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const (
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haveData16 = 1 << iota
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haveData32
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haveAddr16
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haveAddr32
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haveXacquire
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haveXrelease
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haveLock
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haveHintTaken
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haveHintNotTaken
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haveBnd
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)
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var prefixBits uint32
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prefix := ""
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for _, p := range inst.Prefix {
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if p == 0 {
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break
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}
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if p&0xFF == 0xF3 {
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prefixBits &^= haveBnd
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}
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if p&(PrefixImplicit|PrefixIgnored) != 0 {
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continue
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}
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switch p {
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default:
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prefix += strings.ToLower(p.String()) + " "
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case PrefixCS, PrefixDS, PrefixES, PrefixFS, PrefixGS, PrefixSS:
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if inst.Op == 0 {
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prefix += strings.ToLower(p.String()) + " "
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}
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case PrefixREPN:
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prefix += "repne "
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case PrefixLOCK:
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prefixBits |= haveLock
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case PrefixData16, PrefixDataSize:
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prefixBits |= haveData16
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case PrefixData32:
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prefixBits |= haveData32
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case PrefixAddrSize, PrefixAddr16:
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prefixBits |= haveAddr16
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case PrefixAddr32:
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prefixBits |= haveAddr32
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case PrefixXACQUIRE:
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prefixBits |= haveXacquire
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case PrefixXRELEASE:
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prefixBits |= haveXrelease
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case PrefixPT:
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prefixBits |= haveHintTaken
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case PrefixPN:
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prefixBits |= haveHintNotTaken
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case PrefixBND:
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prefixBits |= haveBnd
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}
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}
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switch inst.Op {
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case JMP:
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if inst.Opcode>>24 == 0xEB {
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prefixBits &^= haveBnd
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}
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case RET, LRET:
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prefixBits &^= haveData16 | haveData32
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}
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if prefixBits&haveXacquire != 0 {
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prefix += "xacquire "
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}
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if prefixBits&haveXrelease != 0 {
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prefix += "xrelease "
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}
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if prefixBits&haveLock != 0 {
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prefix += "lock "
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}
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if prefixBits&haveBnd != 0 {
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prefix += "bnd "
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}
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if prefixBits&haveHintTaken != 0 {
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prefix += "hint-taken "
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}
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if prefixBits&haveHintNotTaken != 0 {
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prefix += "hint-not-taken "
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}
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if prefixBits&haveAddr16 != 0 {
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prefix += "addr16 "
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}
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if prefixBits&haveAddr32 != 0 {
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prefix += "addr32 "
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}
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if prefixBits&haveData16 != 0 {
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prefix += "data16 "
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}
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if prefixBits&haveData32 != 0 {
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prefix += "data32 "
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}
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if inst.Op == 0 {
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if prefix == "" {
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return "<no instruction>"
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}
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return prefix[:len(prefix)-1]
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}
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var args []string
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for _, a := range iargs {
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if a == nil {
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break
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}
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args = append(args, intelArg(&inst, a))
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}
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var op string
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switch inst.Op {
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case NOP:
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if inst.Opcode>>24 == 0x0F {
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if inst.DataSize == 16 {
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args = append(args, "ax")
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} else {
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args = append(args, "eax")
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}
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}
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case BLENDVPD, BLENDVPS, PBLENDVB:
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args = args[:2]
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case INT:
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if inst.Opcode>>24 == 0xCC {
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args = nil
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op = "int3"
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}
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case LCALL, LJMP:
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if len(args) == 2 {
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args[0], args[1] = args[1], args[0]
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}
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case FCHS, FABS, FTST, FLDPI, FLDL2E, FLDLG2, F2XM1, FXAM, FLD1, FLDL2T, FSQRT, FRNDINT, FCOS, FSIN:
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if len(args) == 0 {
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args = append(args, "st0")
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}
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case FPTAN, FSINCOS, FUCOMPP, FCOMPP, FYL2X, FPATAN, FXTRACT, FPREM1, FPREM, FYL2XP1, FSCALE:
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if len(args) == 0 {
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args = []string{"st0", "st1"}
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}
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case FST, FSTP, FISTTP, FIST, FISTP, FBSTP:
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if len(args) == 1 {
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args = append(args, "st0")
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}
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case FLD, FXCH, FCOM, FCOMP, FIADD, FIMUL, FICOM, FICOMP, FISUBR, FIDIV, FUCOM, FUCOMP, FILD, FBLD, FADD, FMUL, FSUB, FSUBR, FISUB, FDIV, FDIVR, FIDIVR:
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if len(args) == 1 {
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args = []string{"st0", args[0]}
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}
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case MASKMOVDQU, MASKMOVQ, XLATB, OUTSB, OUTSW, OUTSD:
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FixSegment:
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for i := len(inst.Prefix) - 1; i >= 0; i-- {
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p := inst.Prefix[i] & 0xFF
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switch p {
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case PrefixCS, PrefixES, PrefixFS, PrefixGS, PrefixSS:
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if inst.Mode != 64 || p == PrefixFS || p == PrefixGS {
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args = append(args, strings.ToLower((inst.Prefix[i] & 0xFF).String()))
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break FixSegment
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}
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case PrefixDS:
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if inst.Mode != 64 {
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break FixSegment
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}
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}
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}
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}
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if op == "" {
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op = intelOp[inst.Op]
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}
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if op == "" {
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op = strings.ToLower(inst.Op.String())
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}
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if args != nil {
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op += " " + strings.Join(args, ", ")
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}
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return prefix + op
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}
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func intelArg(inst *Inst, arg Arg) string {
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switch a := arg.(type) {
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case Imm:
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if inst.Mode == 32 {
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return fmt.Sprintf("%#x", uint32(a))
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}
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if Imm(int32(a)) == a {
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return fmt.Sprintf("%#x", int64(a))
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}
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return fmt.Sprintf("%#x", uint64(a))
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case Mem:
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if a.Base == EIP {
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a.Base = RIP
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}
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prefix := ""
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switch inst.MemBytes {
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case 1:
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prefix = "byte "
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case 2:
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prefix = "word "
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case 4:
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prefix = "dword "
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case 8:
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prefix = "qword "
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case 16:
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prefix = "xmmword "
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}
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switch inst.Op {
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case INVLPG:
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prefix = "byte "
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case STOSB, MOVSB, CMPSB, LODSB, SCASB:
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prefix = "byte "
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case STOSW, MOVSW, CMPSW, LODSW, SCASW:
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prefix = "word "
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case STOSD, MOVSD, CMPSD, LODSD, SCASD:
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prefix = "dword "
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case STOSQ, MOVSQ, CMPSQ, LODSQ, SCASQ:
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prefix = "qword "
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case LAR:
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prefix = "word "
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case BOUND:
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if inst.Mode == 32 {
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prefix = "qword "
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} else {
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prefix = "dword "
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}
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case PREFETCHW, PREFETCHNTA, PREFETCHT0, PREFETCHT1, PREFETCHT2, CLFLUSH:
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prefix = "zmmword "
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}
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switch inst.Op {
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case MOVSB, MOVSW, MOVSD, MOVSQ, CMPSB, CMPSW, CMPSD, CMPSQ, STOSB, STOSW, STOSD, STOSQ, SCASB, SCASW, SCASD, SCASQ, LODSB, LODSW, LODSD, LODSQ:
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switch a.Base {
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case DI, EDI, RDI:
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if a.Segment == ES {
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a.Segment = 0
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}
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case SI, ESI, RSI:
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if a.Segment == DS {
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a.Segment = 0
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}
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}
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case LEA:
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a.Segment = 0
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default:
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switch a.Base {
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case SP, ESP, RSP, BP, EBP, RBP:
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if a.Segment == SS {
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a.Segment = 0
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}
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default:
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if a.Segment == DS {
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a.Segment = 0
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}
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}
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}
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if inst.Mode == 64 && a.Segment != FS && a.Segment != GS {
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a.Segment = 0
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}
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prefix += "ptr "
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if a.Segment != 0 {
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prefix += strings.ToLower(a.Segment.String()) + ":"
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}
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prefix += "["
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if a.Base != 0 {
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prefix += intelArg(inst, a.Base)
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}
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if a.Scale != 0 && a.Index != 0 {
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if a.Base != 0 {
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prefix += "+"
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}
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prefix += fmt.Sprintf("%s*%d", intelArg(inst, a.Index), a.Scale)
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}
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if a.Disp != 0 {
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if prefix[len(prefix)-1] == '[' && (a.Disp >= 0 || int64(int32(a.Disp)) != a.Disp) {
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prefix += fmt.Sprintf("%#x", uint64(a.Disp))
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} else {
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prefix += fmt.Sprintf("%+#x", a.Disp)
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}
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}
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prefix += "]"
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return prefix
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case Rel:
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return fmt.Sprintf(".%+#x", int64(a))
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case Reg:
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if int(a) < len(intelReg) && intelReg[a] != "" {
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return intelReg[a]
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}
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}
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return strings.ToLower(arg.String())
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}
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var intelOp = map[Op]string{
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JAE: "jnb",
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JA: "jnbe",
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JGE: "jnl",
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JNE: "jnz",
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JG: "jnle",
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JE: "jz",
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SETAE: "setnb",
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SETA: "setnbe",
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SETGE: "setnl",
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SETNE: "setnz",
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SETG: "setnle",
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SETE: "setz",
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CMOVAE: "cmovnb",
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CMOVA: "cmovnbe",
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CMOVGE: "cmovnl",
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CMOVNE: "cmovnz",
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CMOVG: "cmovnle",
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CMOVE: "cmovz",
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LCALL: "call far",
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LJMP: "jmp far",
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LRET: "ret far",
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ICEBP: "int1",
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MOVSD_XMM: "movsd",
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XLATB: "xlat",
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}
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var intelReg = [...]string{
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F0: "st0",
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F1: "st1",
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F2: "st2",
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F3: "st3",
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F4: "st4",
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F5: "st5",
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F6: "st6",
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F7: "st7",
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M0: "mmx0",
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M1: "mmx1",
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M2: "mmx2",
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M3: "mmx3",
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M4: "mmx4",
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M5: "mmx5",
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M6: "mmx6",
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M7: "mmx7",
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X0: "xmm0",
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X1: "xmm1",
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X2: "xmm2",
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X3: "xmm3",
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X4: "xmm4",
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X5: "xmm5",
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X6: "xmm6",
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X7: "xmm7",
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X8: "xmm8",
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X9: "xmm9",
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X10: "xmm10",
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X11: "xmm11",
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X12: "xmm12",
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X13: "xmm13",
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X14: "xmm14",
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X15: "xmm15",
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// TODO: Maybe the constants are named wrong.
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SPB: "spl",
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BPB: "bpl",
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SIB: "sil",
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DIB: "dil",
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R8L: "r8d",
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R9L: "r9d",
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R10L: "r10d",
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R11L: "r11d",
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R12L: "r12d",
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R13L: "r13d",
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R14L: "r14d",
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R15L: "r15d",
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}
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