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https://github.com/beego/bee.git
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307 lines
8.5 KiB
Go
307 lines
8.5 KiB
Go
package proc
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import (
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"encoding/binary"
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"github.com/go-delve/delve/pkg/dwarf/frame"
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"github.com/go-delve/delve/pkg/dwarf/op"
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"golang.org/x/arch/x86/x86asm"
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)
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// Arch defines an interface for representing a
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// CPU architecture.
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type Arch interface {
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PtrSize() int
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BreakpointInstruction() []byte
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BreakpointSize() int
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DerefTLS() bool
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FixFrameUnwindContext(fctxt *frame.FrameContext, pc uint64, bi *BinaryInfo) *frame.FrameContext
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RegSize(uint64) int
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RegistersToDwarfRegisters(regs Registers, staticBase uint64) op.DwarfRegisters
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GoroutineToDwarfRegisters(*G) op.DwarfRegisters
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}
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// AMD64 represents the AMD64 CPU architecture.
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type AMD64 struct {
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ptrSize int
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breakInstruction []byte
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breakInstructionLen int
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gStructOffset uint64
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hardwareBreakpointUsage []bool
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goos string
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// crosscall2fn is the DIE of crosscall2, a function used by the go runtime
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// to call C functions. This function in go 1.9 (and previous versions) had
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// a bad frame descriptor which needs to be fixed to generate good stack
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// traces.
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crosscall2fn *Function
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// sigreturnfn is the DIE of runtime.sigreturn, the return trampoline for
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// the signal handler. See comment in FixFrameUnwindContext for a
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// description of why this is needed.
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sigreturnfn *Function
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}
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const (
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amd64DwarfIPRegNum uint64 = 16
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amd64DwarfSPRegNum uint64 = 7
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amd64DwarfBPRegNum uint64 = 6
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)
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// AMD64Arch returns an initialized AMD64
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// struct.
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func AMD64Arch(goos string) *AMD64 {
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var breakInstr = []byte{0xCC}
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return &AMD64{
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ptrSize: 8,
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breakInstruction: breakInstr,
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breakInstructionLen: len(breakInstr),
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hardwareBreakpointUsage: make([]bool, 4),
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goos: goos,
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}
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}
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// PtrSize returns the size of a pointer
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// on this architecture.
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func (a *AMD64) PtrSize() int {
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return a.ptrSize
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}
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// BreakpointInstruction returns the Breakpoint
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// instruction for this architecture.
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func (a *AMD64) BreakpointInstruction() []byte {
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return a.breakInstruction
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}
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// BreakpointSize returns the size of the
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// breakpoint instruction on this architecture.
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func (a *AMD64) BreakpointSize() int {
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return a.breakInstructionLen
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}
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// DerefTLS returns true if the value of regs.TLS()+GStructOffset() is a
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// pointer to the G struct
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func (a *AMD64) DerefTLS() bool {
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return a.goos == "windows"
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}
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const (
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crosscall2SPOffsetBad = 0x8
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crosscall2SPOffsetWindows = 0x118
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crosscall2SPOffsetNonWindows = 0x58
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)
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// FixFrameUnwindContext adds default architecture rules to fctxt or returns
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// the default frame unwind context if fctxt is nil.
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func (a *AMD64) FixFrameUnwindContext(fctxt *frame.FrameContext, pc uint64, bi *BinaryInfo) *frame.FrameContext {
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if a.sigreturnfn == nil {
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a.sigreturnfn = bi.LookupFunc["runtime.sigreturn"]
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}
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if fctxt == nil || (a.sigreturnfn != nil && pc >= a.sigreturnfn.Entry && pc < a.sigreturnfn.End) {
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//if true {
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// When there's no frame descriptor entry use BP (the frame pointer) instead
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// - return register is [bp + a.PtrSize()] (i.e. [cfa-a.PtrSize()])
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// - cfa is bp + a.PtrSize()*2
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// - bp is [bp] (i.e. [cfa-a.PtrSize()*2])
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// - sp is cfa
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// When the signal handler runs it will move the execution to the signal
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// handling stack (installed using the sigaltstack system call).
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// This isn't a proper stack switch: the pointer to g in TLS will still
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// refer to whatever g was executing on that thread before the signal was
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// received.
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// Since go did not execute a stack switch the previous value of sp, pc
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// and bp is not saved inside g.sched, as it normally would.
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// The only way to recover is to either read sp/pc from the signal context
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// parameter (the ucontext_t* parameter) or to unconditionally follow the
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// frame pointer when we get to runtime.sigreturn (which is what we do
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// here).
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return &frame.FrameContext{
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RetAddrReg: amd64DwarfIPRegNum,
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Regs: map[uint64]frame.DWRule{
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amd64DwarfIPRegNum: frame.DWRule{
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Rule: frame.RuleOffset,
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Offset: int64(-a.PtrSize()),
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},
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amd64DwarfBPRegNum: frame.DWRule{
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Rule: frame.RuleOffset,
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Offset: int64(-2 * a.PtrSize()),
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},
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amd64DwarfSPRegNum: frame.DWRule{
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Rule: frame.RuleValOffset,
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Offset: 0,
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},
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},
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CFA: frame.DWRule{
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Rule: frame.RuleCFA,
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Reg: amd64DwarfBPRegNum,
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Offset: int64(2 * a.PtrSize()),
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},
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}
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}
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if a.crosscall2fn == nil {
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a.crosscall2fn = bi.LookupFunc["crosscall2"]
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}
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if a.crosscall2fn != nil && pc >= a.crosscall2fn.Entry && pc < a.crosscall2fn.End {
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rule := fctxt.CFA
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if rule.Offset == crosscall2SPOffsetBad {
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switch a.goos {
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case "windows":
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rule.Offset += crosscall2SPOffsetWindows
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default:
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rule.Offset += crosscall2SPOffsetNonWindows
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}
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}
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fctxt.CFA = rule
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}
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// We assume that RBP is the frame pointer and we want to keep it updated,
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// so that we can use it to unwind the stack even when we encounter frames
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// without descriptor entries.
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// If there isn't a rule already we emit one.
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if fctxt.Regs[amd64DwarfBPRegNum].Rule == frame.RuleUndefined {
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fctxt.Regs[amd64DwarfBPRegNum] = frame.DWRule{
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Rule: frame.RuleFramePointer,
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Reg: amd64DwarfBPRegNum,
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Offset: 0,
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}
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}
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return fctxt
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}
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// RegSize returns the size (in bytes) of register regnum.
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// The mapping between hardware registers and DWARF registers is specified
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// in the System V ABI AMD64 Architecture Processor Supplement page 57,
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// figure 3.36
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// https://www.uclibc.org/docs/psABI-x86_64.pdf
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func (a *AMD64) RegSize(regnum uint64) int {
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// XMM registers
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if regnum > amd64DwarfIPRegNum && regnum <= 32 {
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return 16
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}
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// x87 registers
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if regnum >= 33 && regnum <= 40 {
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return 10
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}
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return 8
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}
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// The mapping between hardware registers and DWARF registers is specified
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// in the System V ABI AMD64 Architecture Processor Supplement page 57,
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// figure 3.36
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// https://www.uclibc.org/docs/psABI-x86_64.pdf
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var asm64DwarfToHardware = map[int]x86asm.Reg{
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0: x86asm.RAX,
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1: x86asm.RDX,
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2: x86asm.RCX,
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3: x86asm.RBX,
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4: x86asm.RSI,
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5: x86asm.RDI,
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8: x86asm.R8,
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9: x86asm.R9,
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10: x86asm.R10,
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11: x86asm.R11,
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12: x86asm.R12,
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13: x86asm.R13,
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14: x86asm.R14,
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15: x86asm.R15,
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}
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var amd64DwarfToName = map[int]string{
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17: "XMM0",
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18: "XMM1",
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19: "XMM2",
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20: "XMM3",
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21: "XMM4",
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22: "XMM5",
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23: "XMM6",
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24: "XMM7",
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25: "XMM8",
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26: "XMM9",
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27: "XMM10",
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28: "XMM11",
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29: "XMM12",
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30: "XMM13",
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31: "XMM14",
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32: "XMM15",
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33: "ST(0)",
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34: "ST(1)",
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35: "ST(2)",
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36: "ST(3)",
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37: "ST(4)",
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38: "ST(5)",
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39: "ST(6)",
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40: "ST(7)",
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49: "Eflags",
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50: "Es",
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51: "Cs",
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52: "Ss",
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53: "Ds",
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54: "Fs",
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55: "Gs",
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58: "Fs_base",
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59: "Gs_base",
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64: "MXCSR",
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65: "CW",
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66: "SW",
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}
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func maxAmd64DwarfRegister() int {
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max := int(amd64DwarfIPRegNum)
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for i := range asm64DwarfToHardware {
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if i > max {
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max = i
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}
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}
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for i := range amd64DwarfToName {
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if i > max {
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max = i
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}
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}
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return max
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}
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// RegistersToDwarfRegisters converts hardware registers to the format used
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// by the DWARF expression interpreter.
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func (a *AMD64) RegistersToDwarfRegisters(regs Registers, staticBase uint64) op.DwarfRegisters {
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dregs := make([]*op.DwarfRegister, maxAmd64DwarfRegister()+1)
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dregs[amd64DwarfIPRegNum] = op.DwarfRegisterFromUint64(regs.PC())
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dregs[amd64DwarfSPRegNum] = op.DwarfRegisterFromUint64(regs.SP())
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dregs[amd64DwarfBPRegNum] = op.DwarfRegisterFromUint64(regs.BP())
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for dwarfReg, asmReg := range asm64DwarfToHardware {
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v, err := regs.Get(int(asmReg))
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if err == nil {
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dregs[dwarfReg] = op.DwarfRegisterFromUint64(v)
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}
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}
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for _, reg := range regs.Slice(true) {
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for dwarfReg, regName := range amd64DwarfToName {
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if regName == reg.Name {
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dregs[dwarfReg] = op.DwarfRegisterFromBytes(reg.Bytes)
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}
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}
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}
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return op.DwarfRegisters{StaticBase: staticBase, Regs: dregs, ByteOrder: binary.LittleEndian, PCRegNum: amd64DwarfIPRegNum, SPRegNum: amd64DwarfSPRegNum, BPRegNum: amd64DwarfBPRegNum}
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}
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// GoroutineToDwarfRegisters extract the saved DWARF registers from a parked
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// goroutine in the format used by the DWARF expression interpreter.
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func (a *AMD64) GoroutineToDwarfRegisters(g *G) op.DwarfRegisters {
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dregs := make([]*op.DwarfRegister, amd64DwarfIPRegNum+1)
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dregs[amd64DwarfIPRegNum] = op.DwarfRegisterFromUint64(g.PC)
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dregs[amd64DwarfSPRegNum] = op.DwarfRegisterFromUint64(g.SP)
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dregs[amd64DwarfBPRegNum] = op.DwarfRegisterFromUint64(g.BP)
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return op.DwarfRegisters{StaticBase: g.variable.bi.staticBase, Regs: dregs, ByteOrder: binary.LittleEndian, PCRegNum: amd64DwarfIPRegNum, SPRegNum: amd64DwarfSPRegNum, BPRegNum: amd64DwarfBPRegNum}
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}
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